Rob gave a talk on mapping dataflow programs to FPGAs at the Scottish Programming Language Seminar series at the University of the West of Scotland.
FPGAs are unlike fixed, conventional processor architectures. FPGAs are programmable, meaning that logic gates and special purpose hardware blocks can be configured to precisely meet the needs of algorithms. Dataflow languages map naturally to the distributed hardware layout on FPGA fabric, and offer a high level programming abstraction to design FPGA accelerators.
This talk will cover dataflow language models, from synchronous actors supporting signal processing, to asynchronous FSM actors supporting complex non-trivial algorithms. I will demonstrate how a hardware cost modeller is used in conjunction with a graphical program refactoring tool we have developed, to trade off throughput time with space. Our Petri Net dataflow abstraction aids parallelism discovery of stateful actors, to increase the generality of the program transformations. I will briefly present our image processing DSL, showing how the Dataflow Process Network model is an effective intermediary between higher order algorithm skeletons and FPGAs.