Border Patrol logo, a Border Collie


Border Patrol is an EPSRC funded research project as part of the Trust, Identity, Privacy and Security in the Digital Economy call. We are a collaborative project between the Universities of Glasgow, Heriot-Watt, and Imperial College London.

Our goal is to make the design of hardware systems, and in particular smart devices, resiliant against hidden malicious functionality by ensuring that devices only do what is expected of them. It is an ambitious project that combines state-of-the-art advances in type theory and compiler technology, and applies them to hardware design. You can read more about the ideas behind the project here.

We will focus our work on FPGA-based smart devices, and to ensure that our ideas can gain traction, we will work closely with several Industrial partners. We are working with Xilinx Inc., one of the main FPGA vendors, to integrate our approach into their toolchain, and we are working closely with our other partners, EDF and ABB, on requirements capture and standardisation.

This is a very exciting project and we believe that it will lead to greatly improved security of smart devices, and in fact to improved productivity and increased reliability in hardware design in general.

Recent Posts

Posts Date Created Categories
A Typing Discipline for Hardware Interfaces. April 1, 2019 idris,dependent-types,glasgow,paper,ecoop
Value-Dependent Session Design in a Dependently-Typed Language. March 7, 2019 idris,dependent-types,session-types,paper,places,tdvcs,glasgow
Revisiting Type-Driven Design of Communicating Systems February 5, 2019 idris,hardware,substructural-type-systems,session-types,dependent-types,glasgow,plug,tdd
Type-Driven Development of SoC Architectures. December 11, 2018 idris,soc,hardware,substructural-type-systems,dependent-types,glasgow,tdd,systems
Type-Driven Development of SoC Architectures. October 17, 2018 idris,soc,hardware,substructural-type-systems,dependent-types,glasgow,tdd,spls
Type-Systems for Describing System-on-a-Chip Architectures. July 12, 2018 idris,soc,hardware,linear-types,dependent-types,border-patrol,tdd,pl-interest,glasgow,talks
Summer Quarterly Meeting June 27, 2018 news,website,heriot-watt,imperial,glasgow
Graph Reduction Hardware Revisited June 14, 2018 functional programming,FPGAs,Haskell,graph reduction
A Type-System for describing System-on-a-Chip Architectures. April 5, 2018 idris,soc,hardware,linear-types,dependent-types,border-patrol,tdd,stacs-fp,glasgow,talks
Project Visit Xilinx Edinburgh March 28, 2018 news,website,visit,heriot-watt,glasgow
A Type-System for describing the Structural Topology of System-on-a-Chip Architectures. February 28, 2018 idris,soc,hardware,linear-types,dependent-types,border-patrol,tdd,msp101,glasgow,talks
Winter Quaterly Meeting February 19, 2018 news,website,heriot-watt,imperial,glasgow
Designing Hardware using Session Types and Dependent Types---A First Look October 11, 2017 glasgow,idris,session-types,border-patrol,tdd,spls,talks
Project Visit Xilinx Dublin October 3, 2017 news,website,visit,heriot-watt,glasgow,imperial
Autumn Quaterly Meeting September 29, 2017 news,website,heriot-watt,imperial,glasgow
Border Patrol':' Improving Hardware Security through Type-Aware Systems Design September 12, 2017 idris,glasgow,talks,arm-summit
Mapping dataflow programs to FPGAs June 26, 2017 fpga,dataflow,talks
Technical Kick-Off Launch. June 12, 2017 news,website,heriot-watt,imperial,glasgow
Launch of Project Website. May 22, 2017 news,website
High Level DSLs for HPC, GPUs and FPGAs; Are There DSLs? March 29, 2017 dsls,fpga,talks

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